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Preliminary W25S243A 64K x 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W25S243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 x 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both PentiumTM burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduces power dissipation. This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
* * * * * * *
Synchronous operation High-speed access time: 12 nS Single +3.3V power supply Individual byte write capability 3.3V LVTTL compatible I/O Clock-controlled and registered input Asynchronous output enable
* * * * *
Pipelined/non-pipelined data output capability Supports snooze mode (low-power state) Internal burst counter supports Intel burst (Interleaved) mode & linear burst mode Supports 2T/1T mode Packaged in 128-pin QFP and TQFP
BLOCK DIAGRAM
A(15:0)
INPUT REGISTER 64K X 64 CORE ARRAY
CLK CE(3:1) GW BWE BW(8:1) OE ADSC ADSP ADV LBO FT ZZ CONTROL LOGIC REGISTER DATA I/O REGISTER I/O(64:1)
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Publication Release Date: November 1998 Revision A1
Preliminary W25S243A
PIN CONFIGURATION
V DC D NEN Q C2 C 1 12 28 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 3 9
//// / CV V/ B BB B/ C E S D C W W W WO L 3 S DE8 7 6 5 EK
// / / / AA/ V // B / BBVV B BDDAS W G WWS D W WS S D S E W4 3 S D 2 1 C P V Q
VSSQ I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 VDDQ VSSQ I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 VDDQ VSSQ I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 VDDQ
111 1 11 1 1 11 1 1 11 1 11 1 11 1 1111 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 102 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 65 0123456789012345678901234 / AA AV VAA A AA RAA AAA VVAA A Z V L 1 1 1 DS1 1 1 9 8 S 7 6 5 4 3 DS 2 1 0 Z D V D B54 3 DS2 1 0 DS Q O
VDDQ I/O32 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 VSSQ VDDQ I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 VSSQ VDDQ I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 VSSQ
V/ SF ST Q
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Preliminary W25S243A
PIN DESCRIPTION
SYMBOL A0-A15 I/O1-I/O64 CLK CE1, CE2, CE3 GW BWE BW1- BW8 OE ADV ADSC ADSP ZZ FT TYPE Input, Synchronous I/O, Synchronous Input, Clock Input, Synchronous Input, Synchronous Input, Synchronous Input, Synchronous Input, Asynchronous Input, Synchronous Input, Synchronous Input, Synchronous Input, Asynchronous Input, Static Host address Data Inputs/Outputs Processor host bus clock Chip enables Global write Byte write enable from cache controller Host bus byte enables used with BWE Output enable input Internal burst address counter advance Address status from Chip Set Address status from CPU Snooze pin for low-power state, internal pull low Connected to VSSQ: Device operates in flowthrough (non-pipelined) mode. Connected to VDDQ or unconnected: Device operates in pipelined mode. LBO Input, Static Lower address burst order Connected to VSSQ: Device is in linear mode. Connected to VDDQ or unconnected: Device is in non-linear mode. VDDQ VSSQ VDD VSS RSV NC I/O power supply I/O ground Power supply Ground Reserved pin, don't use these pins No connection DESCRIPTION
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Publication Release Date: November 1998 Revision A1
Preliminary W25S243A
FUNCTIONAL DESCRIPTION
The W25S243A is a synchronous-burst pipelined SRAM designed for use in high-end personal computers. It supports two burst address sequences for IntelTM systems (Interleaved mode) and linear mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC and the burst counter is incremented whenever ADV is sampled low. The device can also be switched to non-pipelined mode if necessary.
BURST ADDRESS SEQUENCE
INTEL SYSTEM ( LBO = VDDQ) A[1:0] External Start Address Second Address Third Address Fourth Address 00 01 10 11 A[1:0] 01 00 11 10 A[1:0] 10 11 00 01 A[1:0] 11 10 01 00 LINEAR MODE ( LBO = VSSQ) A[1:0] 00 01 10 11 A[1:0] 01 10 11 00 A[1:0] 10 11 00 01 A[1:0] 11 00 01 10
The device supports several types of write mode operations. BWE and BW [8:1] support individual byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is used to override the byte enable signals and allows the cache controller to write all bytes to the SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM latches both data and valid byte enable signals from the processor.
TRUTH TABLE
CYCLE Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read ADDRESS USED No No No No No External External Next Next Next Next Current Current Current Current CE1 1 0 0 0 0 0 0 X X 1 1 X X 1 1 CE2 X X 0 X 0 1 1 X X X X X X X X CE3 X 1 X 1 X 0 0 X X X X X X X X ADSP X 0 0 1 1 0 1 1 1 X X 1 1 X X ADSC 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 ADV X X X X X X X 0 0 0 0 1 1 1 1 OE X X X X X X X 1 0 1 0 1 0 1 0 DATA Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z D-Out Hi-Z D-Out Hi-Z D-Out Hi-Z D-Out WRITE* X X X X X X Read Read Read Read Read Read Read Read Read
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Preliminary W25S243A
Truth Table, continued CYCLE Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write ADDRESS USED Current Current External Next Next Current Current CE1 X 1 0 X 1 X 1 CE2 X X 1 X X X X CE3 X X 0 X X X X ADSP 1 X 1 1 X 1 X ADSC 1 1 0 1 1 1 1 ADV 1 1 X 0 0 1 1 OE X X X X X X X DATA Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z WRITE* Write Write Write Write Write Write Write
Notes: 1. For a detailed definition of read/write, see the Write Table below. 2. An "X" means don't care, "1" means logic high, and "0" means logic low. 3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to the bus clock except for the OE pin. 4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timings are met.
WRITE TABLE
READ/WRITE FUNCTION Read Read Write byte 1 I/O1-I/O8 Write byte 2 I/O9-I/O16 Write byte 2, byte 1 Write byte 3 I/O17-I/O24 Write byte 3, byte 1 Write byte 3, byte 2 Write byte 3, byte 2, byte 1 Write byte 4, I/O25-I/O32 Write byte 4, byte 1 Write byte 4, byte 2 Write byte 4, byte 2, byte 1 Write byte 4, byte 3 Write byte 4, byte 3, byte 1 Write byte 4, byte 3, byte 2 Write byte 4, byte 3, byte 2, byte 1 Write byte 5, I/O33-I/O40 Write byte 5, byte 1
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1
X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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Publication Release Date: November 1998 Revision A1
Preliminary W25S243A
Write Table, continued
READ/WRITE FUNCTION Write byte 5, byte 2 Write byte 5, byte 2, byte 1 Write byte 5, byte 3 Write byte 5, byte 3, byte 1 Write byte 5, byte 3, byte 2 Write byte 5, byte 3, byte 2, byte 1 Write byte 5, byte 4 Write byte 5, byte 4, byte 1 Write byte 5, byte 4, byte 2 Write byte 5, byte 4, byte 2, byte 1 Write byte 5, byte 4, byte 3 Write byte 5, byte 4, byte 3, byte 1 Write byte 5, byte 4, byte 3, byte 2 Write byte 5, byte 4, byte 3, byte 2, byte 1 Write byte 6 Write byte 6, byte 1 Write byte 6, byte 2 Write byte 6, byte 2, byte 1 ..... and so on ..... Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 2, byte 1 Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3 Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3, byte 1 Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3, byte 2 Write all bytes Write all bytes
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 1 1 1 1 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 0 0 0 0 0 x
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 0 0 0 0 0 x
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ... 0 0 0 0 0 x
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 ... 0 0 0 0 0 x
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 ... 0 0 0 0 0 x
1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 ... 0 0 0 0 0 x
1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ... 1 0 0 0 0 x
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 ... 0 1 1 0 0 x
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ... 0 1 0 1 0 x
The ZZ state is a low-power state in which the device consumes less power than in the unselected mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the ZZ pin low for a set period of time will wake up the SRAM again. While the SRAM is in ZZ mode, data retention is guaranteed, but the chip will not monitor any input signal except for the ZZ pin. In the unselected mode, on the other hand, all the input signals are monitored.
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Preliminary W25S243A
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Core Supply Voltage to Vss I/O Supply Voltage to Vss Input/Output to VSSQ Potential Allowable Power Dissipation Storage Temperature Operating Temperature RATING -0.5 to 4.6 -0.5 to 4.6 VSSQ -0.5 to VDDQ +0.5 1.0 -65 to 150 0 to +70 UNIT V V V W C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Operating Characteristics
(VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70 C)
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Current Standby Current
SYM. VIL VIH ILI ILO
TEST CONDITIONS VIN = VSSQ to VDDQ VI/O = VSSQ to VDDQ, and data I/O pins in high-Z state defined in truth table IOL = +8.0 mA IOH = -4.0 mA TCYC min. , I/O = 0 mA Unselected mode defined in truth table, VIN, VIO = VIH (min.) /VIL (max.) TCYC min. ZZ mode, TCYC min.
MIN. -0.5 +2.0 -10 -10
TYP. -
MAX. +0.8 VDD +0.3 +10 + 10
UNIT V V A A
VOL VOH IDD ISB
2.4 -
-
0.4 350 80
V V mA mA
ZZ Mode Current
IZZ
-
-
5
mA
Note: Typical characteristics are measured at VDD = 3.3V, TA = 25 C.
CAPACITANCE
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/Output Capacitance
SYM. CIN CI/O
CONDITIONS VIN = 0V VOUT = 0V
MAX. 6 8
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
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Publication Release Date: November 1998 Revision A1
Preliminary W25S243A
AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 2 nS 1.5V CL = 30 pF, IOH/IOL = -4 mA/8 mA CONDITIONS
AC Test Loads and Waveform
RL = 50 ohm VL = 1.5V OUTPUT Zo = 50 ohm 30 pF Including Jig and Scope
R1 320 ohm 3.3V OUTPUT 5 pF Including Jig and Scope R2 350 ohm
(For T KHZ, TKLZ, TOHZ, TOLZ, measurement)
3.0V 0V 2 nS
90% 10% 10%
90%
2 nS
AC Timing Characteristics
(VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70 C, all timings measured in pipelined mode)
PARAMETER Add. Setup Time Add. Hold Time Write Data Setup Time Write Data Hold Time
ADV Setup Time ADV Hold Time
SYMBOL TAS TAH TDS TDH TADVS TADVH
W25S243A-12 MIN. 2.5 0.5 2.5 0.5 2.5 0.5 MAX. -
UNIT nS nS nS nS nS nS
NOTES
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Preliminary W25S243A
AC Timing Characteristics, continued
PARAMETER
SYMBOL TADSS TADSH TADCS TADCH TCES TCEH TWS TWH TCYC TKO TKL TKQ TKHZ TKLZ TKX TOE TOHZ TOLZ TOX TZZS TZZR
W25S243A-12 MIN. MAX. 12 15 7 7 100 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 15 6 6 2 0 2 0 0 100
UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
NOTES
ADSP Setup Time ADSP Hold Time ADSC Setup Time ADSC Hold Time CE1 , CE2, CE3 Setup Time CE1 , CE2, CE3 Hold Time GW , BWE X Setup Time GW , BWE X Hold Time
Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock to Output Valid Clock to Output High-Z Clock to Output Low-Z Clock to Output Invalid Output Enable to Output Valid Output Enable to Output High-Z Output Enable to Output Low-Z Output Enable to Output Invalid ZZ Standby Time ZZ Recover Time
Notes:
1 1 1
1 1
2 3
1. These parameters are sampled but not 100% tested 2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active. 3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode. 4. Configuration signals LBO and FT are static and should not be changed during operation.
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Publication Release Date: November 1998 Revision A1
Preliminary W25S243A
TIMING WAVEFORMS
Read Cycle Timing
Single Read CLK TADSS ADSP TADCS TADCH ADSC TADVS ADV TAS A[15:0] TAH RD1 TWS GW TWS BWE TWH TWH RD2 TADVH TADSH TCYC TKH TKL
Burst Read
Unselected
ADSP is blocked by CE1 inactive
ADSC initiated read
Suspend Burst
RD3
BW[4:1] TCES CE1 TCES CE2 TCES CE3 TOE OE TOLZ Data-Out High-Z TKLZ TKQ Data-In High-Z DON'T CARE UNDEFINED 1a TOX TKX 2a 2b 2c 2d 3a TKHZ TKX TOHZ TCEH TCEH CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 TCEH CE1 masks ADSP
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Preliminary W25S243A
Timing Waveforms, continued
Write Cycle Timing
Single Write CLK
TCYC TKH TKL
Burst Write
Write
Unselected
TADSS ADSP
TADSH
ADSP is blocked by CE1 inactive
TADCS ADSC TADVS ADV TAS TAH A[15:0] WR1 TWS GW TWS BWE TWS BW[4:1] TCES CE1 TCES CE2 TCES CE3 TCEH TCEH TCEH
TADCH
ADSC initiated write
TADVH
ADV must be inactive for ADSP write WR2 TWH WR3 GWE allows processor address (and BE=BW) to be pipelined during a writeback
TWH
TWH WR2 CE1 masks ADSP WR3
WR1
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
OE
Data-Out
High-Z TDS TDH BW[4:1] are applied only to first cycle of WR2 2a 2b 2c 2d 3a
Data-In
High-Z
1a
DON'T CARE UNDEFINED
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Publication Release Date: November 1998 Revision A1
Preliminary W25S243A
Timing Waveforms, continued
Read/Write Cycle Timing
Single Read CLK TADSS ADSP TADCS TADCH ADSC TADVS ADV TAS A[15:0] TAH WR1 TWS GW TWS BWE TWH TWH TADVH TADSH
Single Write TCYC TKH TKL
Burst Read
Unselected
ADSP is blocked by CE1 inactive
ADSC initiated read
Suspend Burst
RD1
RD2
TWS TWH BW[4:1] TCES CE1 TCES CE2 TCES CE3 TOE OE TOLZ Data-Out High-Z TKLZ TKQ Data-In High-Z 1a TKHZ TDSTDH 1a TOH 2a 2b 2c TKX 2d TKHZ TOHZ TCEH Unselected with CE3 TCEH CE2 and CE3 only sampled with ADSP or ADSC TCEH WR1 CE1 masks ADSP
DON'T CARE UNDEFINED
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Preliminary W25S243A
Timing Waveforms, continued
ZZ and RD Timing
Single Read CLK TADSS ADSP TADSH TKH TKL TCYC Snooze -with Data Retention Read
ADSC TADVS ADV TAS A[15:0] RD1 TWS GW TWS BWE TWS BW[4:1] TCES CE1 TCES CE2 TCES CE3 TOE OE TOLZ Data-Out High-Z TKLZ TKQ Data-In High-Z 1a TKX TKHZ TOH TOHZ TCEH TCEH TCEH RD TWH RD RD TWH TWH TAH RD2 TADVH
TZZS ZZ
TZZR
DON'T CARE UNDEFINED
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Publication Release Date: November 1998 Revision A1
Preliminary W25S243A
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 12 12 OPERATING CURRENT MAX. (mA) 350 350 STANDBY CURRENT MAX. (mA) 80 80 PACKAGE
W25S243AF-12 W25S243AD-12
Notes
128-pin QFP 128-pin TQFP
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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Preliminary W25S243A
PACKAGE DIMENSIONS
128-pin QFP
HD D
128 103
1
102
E
EH
38
65
39
e
b
64
c A A2 See Detail F Seating Plane A1 y L L1 Detail F
Dimension in inches
Dimension in mm Min. Nom. Max.
Symbol
Min.
Nom.
Max.
A A1 A2 b c D E e HD HE L L1 y
0.134 0.004 0.101 0.107 0.113 0.010 0.010 0.555 0.791 0.10 2.57 0.15 0.10 13.90 19.90 2.72 0.20 0.15
3.40
2.87 0.25 0.25
0.006 0.008 0.004 0.006 0.547 0.551 0.783 0.787 0.020 0.669 0.905 0.023 0.055 0.677 0.913 0.031 0.063
14.00 14.10 20.00 20.10 0.50
0.685 0.921 0.039 0.071 0.004
17.00 23.00 0.60 1.40
17.20 23.20 0.80 1.60
17.40 23.40 1.00 1.80 0.10
0
12
0
12
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Publication Release Date: November 1998 Revision A1
Preliminary W25S243A
Package Dimensions, continued
128-pin TQFP
HD D
128 103
1
102
E
EH
38
65
39
e
b
64
c A
2
A
See Detail F Seating Plane
1
L L1 Detail F
y
A
Dimension in inches
Symbol
Dimension in mm Min. Nom. Max.
Min.
Nom.
Max.
A A1 A2 b c D E e HD HE L L1 y
0.063 0.002 0.053 0.055 0.057 0.011 0.010 0.555 0.791 0.05 1.35 0.15 0.10 13.90 19.90 1.40 0.20 0.15
1.60
1.45 0.27 0.25
0.006 0.008 0.004 0.006 0.547 0.551 0.783 0.787 0.020 0.626 0.862 0.018 0.630 0.866 0.024 0.039
14.00 14.10 20.00 20.10 0.50
0.634 0.870 0.030
15.90 21.90 0.45
16.00 22.00 0.60 1.00
16.10 22.10 0.75
0.004 0 12 0
0.10 12
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Preliminary W25S243A
VERSION HISTORY
VERSION A1 DATE Nov. 1998 PAGE DESCRIPTION Initial Issued
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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Publication Release Date: November 1998 Revision A1

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